Modelsim altera for verilog download8/4/2023 ![]() ** Error: G:/Verilog/uvm_ex1.sv(5): (vlog-2163) Macro ``uvm_info is undefined. ** Error: G:/Verilog/uvm_ex1.sv(3): Cannot open `include file "uvm_macros.svh". Please check the package names or the library search paths on the command line. ![]() This is the error message I get : ** Error: G:/Verilog/uvm_ex1.sv(2): Could not find the package (uvm_pkg).ĭesign read will continue, but expect a cascade of errors after this failure.įurthermore if you experience a vopt-7 error immediately before this error then Ofcouse I can use EDA playground but I was wondering how to do it in Modelsim-Altera while the same can be done on EDA playground using modelsim tool itself. It would be helpful to me if anybody can suggest me something on this. But I have heard that UVM is supported by Modelsim except randomization. I get error when I try to compile the above code. `uvm_info("ID","WELCOME TO UVM",UVM_MEDIUM) I want to compile and simulate this simple UVM example using Modelsim-Altera 10.1d tool. ModelSim-Altera Edition Download - It is designed to support digital designs written in VHDL or Verilog Windows Developer Tools IDE ModelSim-Altera Edition ModelSim-Altera Edition 6.6 It is designed to support digital designs written in VHDL or Verilog 3.2 6 votes Your vote: Latest version: 6.
0 Comments
Leave a Reply.AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |